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Verilog Implementation of Asynchronous FIFO
This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains every aspects of the code. | Verilog HDL and Digital electronics
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Solutions to HDL-Bits
This repo contains HDL-bits solutions. I tried to provide multiple solutions for the same problem, with comments | Verilog HDL
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5-stage piplined RISCV processor
Mini-project for the grading of Digital system design with FPGA course - IISc | year 2024. RISC V 8 bit 5 stage pipelined processor verilog code | Verilog HDL, COA, and FPGA
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16-bit, Radix-4, 2-Stage Signed Booth Multiplier
Designed the Schematics and Layout of a 16-bit signed, radix-4 booth multiplier with a 2-stage pipeline using 45nm GPDK. The maximum operation frequency obtained is 70 MHz | Digital VLSI and Cadence Virtuoso
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Graphing Tool using touch LCD
A graphical calculator through the integration of touch LCD with Tiva Launchpad. Utilized the touch screen capabilities to enable zoom in/out, left, right, top, and bottom functionalities, allowing users to explore detailed views of plotted graphs | Embedded, Tiva Launchpad, and C
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Train Collision avoidance system
Mini-project for the grading of TCP/IP Networking course - IISc year 2023 | Python and TCP
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Verilog implementation of FFT
Input 𝑥 = {𝑥0, 𝑥1, ⋯ , 𝑥7}, Output 𝑋 = {𝑋0, 𝑋1, ⋯ , 𝑋7}, Output 𝑋 is the 8-point FFT of input x | Verilog HDL, Mathematics, and FFT
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Tetris implemented on Arduino UNO
This project implements the classic game of Tetris using a Neopixel LED strip and an Arduino UNO. The player interacts with the game using five push buttons, controlling the movement and rotation of falling tetrominoes within a 10x10 matrix. | Embedded systems, Arduino UNO, and C
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Circles
A fun and intractive page. Hit any alphabetical key and see the magic. | Howler.js
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Candy Museum
A responsive page with candies that is built using bootstrap 4 grid system. | Bootstrap4
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